The present application relates to a clock signal transmission circuit for providing a stable clock signal to an internal circuit.
In a semiconductor integrated circuit device, an internal circuit is operated based on a clock signal generated by a clock signal generation circuit. Such a semiconductor integrated circuit device includes a clock signal transmission circuit. When the semiconductor integrated circuit is activated, the clock signal transmission circuit provides the internal circuit with the clock signal after the clock signal stabilizes. It is required that the clock signal transmission circuit readily provides the internal circuit with a stable clock signal.
In the semiconductor integrated circuit device, a clock signal generation circuit, which uses a crystal oscillator, provides the clock signal via the clock signal transmission circuit to the internal circuit. The internal circuit is operated based on the clock signal.
During activation of the semiconductor integrated circuit device, when power is supplied, various types of settings are initialized. Then, after an original clock signal output from the clock signal generation circuit stabilizes, the clock signal transmission circuit provides the internal circuit with a clock signal. An example of a clock signal transmission circuit in the prior art will now be described with reference to FIG. 1A.
When power is supplied, a clock signal generation circuit (not shown) inputs complementary original clock signals CLKX and /CLKX (“/” represents bar) to terminals X0 and X1, respectively. The original clock signal CLKX is fed to a hysteresis inverter circuit 1, and the original clock signal /CLKX is fed to a NAND circuit 2. An inverter circuit 3 and a transfer gate 4 function when the terminal X1 is used as an output terminal and do not function when the original clock signals CLKX and /CLKX are input to the terminals X0 and X1.
The hysteresis inverter circuit 1 provides the original clock signal CLKX to a register circuit 5 (clock generation unit), which is configured by a flip-flop circuit. The register circuit 5 divides the original clock signal CLKX into two cycles to generate a clock signal CLK. Then, the register circuit 5 outputs and provides the clock signal CLK as an output signal Q to a counter 6 and a clock control unit 7.
The counter 6 is a 16-bit counter for counting the pulses of the output signal Q. When the count becomes 21, the counter 6 provides a selector 8 with an output signal OS11, which is set at a high level. In the same manner, the counter 6 provides the selector 8 with an output signal OS10, which is set at a high level, when the count becomes 210, an output signal OS00, which is set at a high level, when the count becomes 214, and an output signal OS01, which is set at a high level, when the count becomes 216. In response to selection signals SL1 and SL2 respectively provided from register circuits 9a and 9b, one of the output signals OS11 to OS00 is selected as an output signal X, which is provided to a register circuit 10.
The register circuits 9a and 9b respectively provide the selector 8 with the selection signals SL1 and SL2 as data D, which is provided from the CPU 11 via a bus 12. For example, when the selection signals SL1 and SL2 configure the data of “11”, the selector 8 provides the register circuit 10 with the output signal OS11 of the counter 6. When the selection signals SL1 and SL2 configure the data of “00”, the selector 8 provides the register circuit 10 with the output signal OS00 of the counter 6.
When a semiconductor integrated circuit device incorporating the clock signal transmission circuit is activated or reset, the register circuits 5, 9a, and 9b are provided with a reset signal RST. When the reset signal RST is shifted to a low level, the data D, which is stored in the register circuits 9a and 9b is reset to “0”, and the output signal Q of the register circuit 5 is reset to a low level.
The register circuit 10 is provided with the output signal X of the selector 8 as an enable signal EN. When the enable signal EN shifts to a high level, the register circuit 10 provides the clock control unit 7 with an output signal Q having a low level.
When the output signal Q of the register circuit 10 rises to a high level, the clock control unit 7 provides the clock signal CLK output from the register circuit 5 to a CPU 11. The output signal Q of the register circuit 10 is reset by a low level clear signal CL, which is output from the clock control unit 7.
In such a clock signal transmission circuit, when the semiconductor integrated circuit device is activated, the selection signals SL1 and SL2 of the register circuits 9a and 9b are both set at a low level, or “00”, by the reset signal RST.
As a result, the selector 8 provides the register circuit 10 with the output signal OS00 of the counter 6. Accordingly, after 214 pulses of the clock signal CLK are counted during activation, the clock control unit 7 provides the CPU 11 with the clock signal CLK.
Referring to FIG. 1B, the clock signal transmission circuit provides the clock signal CLK, which is generated from the original clock signal CLKX, to the CPU 11 after a wait time T elapses. The wait time T is the time required for stabilization of the original clock signal CLKX, which is generated by the clock signal generation circuit, when the semiconductor integrated circuit is activated.
FIG. 2 shows an example of the wait time T, which is set by the counter 6. When the selection signals SL1 and SL2 are “00” and the cycle of the clock signal CLK is represented by φ, the wait time T is expressed as T=φ×214. When the original clock signal CLKX is 4 MHz, the wait time T is 8.2 msec.
In the same manner, when the selection signals SL1 and SL2 are “10” (SL1=1, SL2=0), the wait time T, which is expressed by φ×216, is 32.8 msec. When the selection signals SL1 and SL2 are “01” (SL1=0, SL2=1), the wait time T, which is expressed by φ×210, is 512 μsec. When the selection signals SL1 and SL2 are “11”, the wait time T, which is expressed by φ×21, is 1.0 μsec.
Therefore, in the clock signal transmission circuit of the prior art, the selection signals SL1 and SL2 are reset to “00” during activation. Thus, the wait time T is 8.2 msec.
After the activation, the data of the register circuits 9a and 9b becomes rewritable by the CPU 11. Accordingly, when resetting an internal circuit, such as the CPU 11, the wait time T can be varied by changing the output signal X of the selector 8 to another output signal of the counter 6 based on predetermined data set for the register circuits 9a and 9b, namely, the selection signals SL1 and SL2.
When the semiconductor integrated circuit undergoes a function test, a scan shift test is conducted with a scan chain, which is formed by series-coupling a group of data holding circuits, such as flip-flop circuits, that are arranged on the semiconductor integrated circuit. The scan shift test is conducted to determine whether or not the data holding circuits are each functioning normally as a shift register.
FIG. 3 shows an example of a scan chain. In a register circuit group of register circuits 13a to 13c, a scan-out terminal SO of one of two register circuits that are arranged near each other on a chip is coupled to a scan-in terminal SI of the other one of the two register circuits. This couples the two register circuits in series. FIG. 3 shows only the three register circuits 13a to 13c. However, an actual scan chain includes thousands of register circuits that are coupled in series.
The register circuits 13a to 13c are provided with a scan mode signal SCAN_MD during a scan mode. Further, the register circuits 13a to 13c are provided via a selector 14 with a scan clock signal SCAN_CK during the scan mode and a normal clock signal CLKP during a normal mode.
The register circuits 13a to 13c are provided with the reset signal RST via an inverter circuit 15. When the reset signal RST rises to a high level, the data stored in each of the register circuits 13a to 13c is reset to, for example, “0”. Input terminal D and output terminal Q in each of the register circuits 13a to 13c are the terminals used in a normal mode.
In such a scan chain, during the scan mode, scan data SIN is input to the scan-in terminal SI of the register circuit 13a, which is in the first stage, and then transferred to the register circuit 13b, which is in the next stage, in accordance with the scan clock signal SCAN_CK. When scan data OUT output from the register circuit in the final stage (i.e., the register circuit 13c in FIG. 3) is identical to the scan data SIN, which is input to the first stage register circuit 13a, this indicates that the register circuits are all functioning normally.
In the clock signal transmission circuit shown in FIG. 1A, during activation, the selection signals SL1 and SL2 output from the register circuits 9a and 9b are reset to “00”. Thus, the wait time T during activation is fixed to the time required for the output signal OS00 of the counter 6 to shift to a high level. More specifically, if the clock signal CLKX is 4 MHz, the wait time T is fixed to 8.2 msec.
In a case in which a user selects and uses a clock signal generation circuit that generates the original clock signal, the wait time T may be reduced depending on differences in the characteristics of the crystal oscillator that configures the clock signal generation circuit.
However, in the clock signal transmission circuit of FIG. 1A, an initial value of the wait time T, that is, the initial values of the register circuits 9a and 9b, are fixed. Thus, even if characteristics of the clock signal generation circuit are such that reduction of the wait time T should be possible, the wait time T may be set such that it is unnecessarily long.
Japanese Laid-Open Patent Publication No. 4-362719 describes a stable oscillation waiting circuit that obtains a predetermined stable oscillation wait time for an operation clock. However, the initial value of the wait time during activation is also fixed in the circuit of the publication.